DocumentCode
608610
Title
Efficient multiplier-free FPGA demonstration of polar-domain multi-symbol-delay-detector (MSDD) for high performance phase recovery of 16-QAM
Author
Tolmachev, Alex ; Tselniker, Igor ; Meltsin, M. ; Sigron, I. ; Nazarathy, Moshe
Author_Institution
Electr. Eng. Dept., Technion - Israel Inst. of Technol., Haifa, Israel
fYear
2013
fDate
17-21 March 2013
Firstpage
1
Lastpage
3
Abstract
We eliminate all multipliers from the MSDD carrier recovery (CR) sub-system without performance penalty. The extreme-low-complexity CR is demonstrated in real-time in FPGA HW.
Keywords
communication complexity; field programmable gate arrays; multiplying circuits; quadrature amplitude modulation; CR sub-system; FPGA HW; MSDD carrier recovery subsystem; QAM; extreme-low-complexity CR; high performance phase recovery; multiplier-free FPGA demonstration; performance penalty; polar-domain multisymbol-delay-detector; Complexity theory; Field programmable gate arrays; Hardware; Optical noise; Phase noise; Real-time systems; Signal to noise ratio;
fLanguage
English
Publisher
ieee
Conference_Titel
Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013
Conference_Location
Anaheim, CA
Print_ISBN
978-1-4799-0457-0
Type
conf
Filename
6532750
Link To Document