A Cycle Count Accurate TLM bus modeling approach

This paper presents an effective Cycle-Count Accurate Transaction Level Modeling (CCA-TLM) and simulation technique for a point-to-point bus. We propose a two-phase bus arbitration model and an FSM-based Composite Master-Slave-pair and Arbiter Transaction (CMSAT) model for efficient and accurate dynamic simulations. This approach is particularly effective for bus architecture validation and contention analysis of complex Multi-Processor System-on-Chip (MPSoC) designs. The experiment results show that the proposed approach performs 23 times faster than the Cycle-Accurate (CA) bus model while maintaining 100% accurate timing information at every transaction boundary.