Well proximity effects on digital cells due to context-variability

As VLSI technology scales toward 45nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. Well proximity effects contribute with a non-negligible amount of time and power variation on recent technology. Therefore the well proximity-based extraction flow has become a candidate to accurately capture the process variations and hence more accurate timing and power results. The more accurate modelling of all digital cell variations effects, the less value of On Chip Variation (OCV) specifically in recent technologies. Reducing OCV value has dramatic effect on timing constrains from design perspective, as reducing OCV means less constraints and hence less power, area and reduce design phase. This paper presents a proposal for a design flow to enhance the manufacturability of the traditional standard cell library. The novel method comprises fully automated well proximity-aware techniques for measuring timing variations in digital cells. The results indicate a ±2% variation across whole library contexts with respect to mean value. Without context awareness, the variations can reach ±20% which implies context aware characterization is a very important factor for achieving accurate results in cell characterization process. This shows the importance of having a variability-aware method that qualifies the libraries to be adopted for circuit designs.