Investigation of shape etching on multi-layer SiO2/poly-Si for 3D NAND architecture

Author

Zusing Yang ; Fang-Hao Hsu ; Lo Yueh Lin ; Hong-Ji Lee ; Nan-Tzu Lian ; Tahone Yang ; Kuang-Chao Chen ; Chih-Yuan Lu

Author_Institution

Technol. Dev. Center, Macronix Int. Co., Ltd., Hsinchu, Taiwan

fYear

2013

fDate

14-16 May 2013

Firstpage

24

Lastpage

26

Abstract

This paper describes a simple and systematic etching approach for the preparation of smooth vertical bit line (BL), stacked with multiple layers of SiO₂ (OX) and poly-Si (PL) films for the use in three-dimensional vertical gate (3DVG) NAND flash application. A successful shape evolution from tapered to acceptable BL profile with sub-10 nm critical dimension (CD) difference between bottom and top PL layers is performed by a recipe consisting of etch-trim-etch processing steps. This novel etch sequence is more advantageous than that of traditional simultaneous etch-deposition process for controlling profile shape of the multi-layer stack in the 3D NAND flash manufacturing.

Keywords

etching; flash memories; lithography; semiconductor industry; 3D NAND architecture; 3D NAND flash manufacturing; 3DVG NAND flash application; critical dimension; shape etching; systematic etching; three-dimensional vertical gate NAND flash application; vertical bit line; Etching; Films; Flash memories; Loading; Shape; Three-dimensional displays; Very large scale integration; 3D NAND; 3DVG NAND; bit line; multi-layer SiO2/Poly-Si; plasma etch;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Manufacturing Conference (ASMC), 2013 24th Annual SEMI

Conference_Location

Saratoga Springs, NY

ISSN

1078-8743

Print_ISBN

978-1-4673-5006-8

Type

conf

DOI

10.1109/ASMC.2013.6552747

Filename

6552747