A novel low-power mixed-mode implementation of weight update in particle PHD filters

Power dissipation and hardware cost are two major design concerns in the hardware implementation of particle probability hypothesis density (PHD) filters, wherein the weight update is a crucial design task due to its complicated operation and sequential nature. In this paper, we propose a novel mixed-mode implementation of the weight update in particle PHD filter, which outperforms its counterpart digital-form implementation in terms of power dissipation and hardware resource consumption. In specific, the mixed-mode implementation uses multiple-input translinear element (MITE) networks to realize the likelihood function of weight update in the analog domain. The MITE networks, which are operated in subthreshold region, contribute to the low-power implementation of the particle PHD filters, and can lead to parallel implementation of the weight update with lower hardware cost. Extensive simulations are conducted with circuit models and parameters from the Taiwan Semiconductor Manufacturing Company (TSMC) 0.18μm CMOS technology library for mixed-mode implementation of weight update, and the results show that the analog errors in this mixed mode implementation are negligible when used to support real-world multi-target tracking.