DocumentCode
617701
Title
Parallel GPU architecture simulation framework exploiting work allocation unit parallelism
Author
Sangpil Lee ; Won Woo Ro
Author_Institution
Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea
fYear
2013
fDate
21-23 April 2013
Firstpage
107
Lastpage
117
Abstract
GPU computing is at the forefront of high-performance computing, and it has greatly affected current studies on parallel software and hardware design because of its massively parallel architecture. Therefore, numerous studies have focused on the utilization of GPUs in various fields. However, studies of GPU architectures are constrained by the lack of a suitable GPU simulator. Previously proposed GPU simulators do not have sufficient simulation speed for advanced software and architecture studies. In this paper, we propose a new parallel simulation framework and a parallel simulation technique called work-group parallel simulation in order to improve the simulation speed for modern many-core GPUs. The proposed framework divides the GPU architecture into parallel and shared components, and it determines which GPU component can be effectively parallelized and can work correctly in multithreaded simulation. In addition, the work-group parallel simulation technique effectively boosts the performance of parallelized GPU simulation by eliminating the synchronization overhead. Experimental results obtained using a simulator with the proposed framework show that the proposed parallel simulation technique has a speed-up of up to 4.15 as compared to an existing sequential GPU simulator on an 8-core machine providing minimized cycle errors.
Keywords
graphics processing units; multi-threading; multiprocessing systems; parallel architectures; synchronisation; GPU component; GPU computing; GPU simulator; hardware design; high-performance computing; many-core GPU; multithreaded simulation; parallel GPU architecture simulation framework; parallel architecture; parallel component; parallel software; parallelized GPU simulation performance; shared component; synchronization overhead elimination; work allocation unit parallelism; work-group parallel simulation technique; Computational modeling; Graphics processing units; Instruction sets; Load modeling; Multiprocessor interconnection; Process control;
fLanguage
English
Publisher
ieee
Conference_Titel
Performance Analysis of Systems and Software (ISPASS), 2013 IEEE International Symposium on
Conference_Location
Austin, TX
Print_ISBN
978-1-4673-5776-0
Electronic_ISBN
978-1-4673-5778-4
Type
conf
DOI
10.1109/ISPASS.2013.6557151
Filename
6557151
Link To Document