Countering PCIe Gen. 3 data transfer rate imperfection using serial data interconnect

Author

Rahnama, B. ; Sari, Ali ; Makvandi, Reza

Author_Institution

Comput. Eng., Eur. Univ. of Letke Gemikonagi, Gemikonagi, Cyprus

fYear

2013

fDate

9-11 May 2013

Firstpage

579

Lastpage

582

Abstract

In high-speed data links, serial communications are replacing parallel communications rapidly. High-speed serial data links include backplane links such as PCI express and computer networking including Ethernet interfaces. This study tries to propose new solution for interconnection switches which use specially in HPC systems using a new jitter free data transfer technique for Serialization and Deserialization channels instead of PC Ie conventional links.

Keywords

local area networks; peripheral interfaces; Ethernet interface; HPC system; PCI express; PCIe Gen. 3 data transfer rate; backplane link; channel deserialization; computer networking; high-speed serial data link; interconnection switches; jitter free data transfer technique; parallel communication; serial communications; serial data interconnect; Lasers; Ports (Computers); Reliability; Synthetic aperture sonar; Gigabit Ethernet; HPC; Mixing Clock with Data; PCIe; Serial Data Link;

fLanguage

English

Publisher

ieee

Conference_Titel

Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE), 2013 International Conference on

Conference_Location

Konya

Print_ISBN

978-1-4673-5612-1

Type

conf

DOI

10.1109/TAEECE.2013.6557339

Filename

6557339