Effect of electrical stresses on digital integrated circuits power integrity

Author

Boyer, A. ; Ben Dhia, S.

Author_Institution

LAAS, Univ. de Toulouse, Toulouse, France

fYear

2013

fDate

12-15 May 2013

Firstpage

1

Lastpage

4

Abstract

Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity of digital integrated circuits and clarifying its origin. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip are combined with electric stress to characterize the influence of aging on power integrity. Simulation based on ICEM modeling modified by an empirical coefficient in order to take into account the circuit aging is proposed to model the evolution of the power integrity induced by device aging.

Keywords

CMOS digital integrated circuits; ageing; integrated circuit modelling; integrated circuit testing; CMOS technology test chip; ICEM modeling; digital integrated circuit power integrity; electrical stresses; electromagnetic emission; empirical coefficient; integrated circuit aging; on-chip measurements; power supply voltage; Aging; Integrated circuit modeling; Power measurement; Power supplies; Stress; Voltage measurement; ICEM modelling; Integrated circuits; accelerated aging; power integrity;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal and Power Integrity (SPI), 2013 17th IEEE Workshop on

Conference_Location

Paris

Print_ISBN

978-1-4673-5678-7

Type

conf

DOI

10.1109/SaPIW.2013.6558327

Filename

6558327