Optimization of Processor-to-Hardware Module Communications on Spaceborne Hybrid FPGA-based Architectures

Satellite on-board processing systems are becoming more important every day, thanks to recent advances in hardware architectures. SpaceCube, developed by engineers at NASA Goddard Space Flight Center and based on Virtex-5 commercial field-programmable gate arrays (FPGAs), is one such satellite on-board processing system. This letter describes how methodologies implemented on the Virtex-5 hardware platform can be designed to optimize the communications between the components and modules within the FPGA, including the main processor. A basic methodology, the Euclidean distance calculation for multispectral data, was implemented and added to a higher level hardware system designed in two different ways: A basic one where the communications with the processor are performed by means of a central bus, and an optimized one where such communications are performed through shared memories. Results show that the overall execution performance is higher than in the analogous software version, although the global computation time is directly and highly influenced by the way communications between the main processor and the FPGA are performed.