Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints

This work addresses the energy efficiency of the memory architecture in safety-critical systems that have to guarantee a given level of service and a minimum lifetime. We specifically target SRAM structures in which decreased reliability manifests itself in terms of the aging induced by NBTI (Negative Bias Temperature Instability), and in which the level of service is represented by the bit-error rate (BER). Our approach is based on the idea of determining an energy-optimal scheduling of supply voltages for the SRAM that satisfy the specified lifetime and BER constraints. The construction of the scheduling leverages semi-empirical models for the quantity of interest (aging, energy, memory performance, error rate) in terms of the supply voltage, and is determined through a search-based algorithm in the corresponding solution space. The optimization framework is embedded into a design space exploration tool that allows browsing the energy/performance/ reliability space for the various desired lifetime/error rate and by varying architectural parameters such operating frequency and memory size.