Ripple 2.0: High quality routability-driven placement via global router integration

Author

Xu He ; Tao Huang ; Wing-Kai Chow ; Jian Kuang ; Ka-Chun Lam ; Wenzan Cai ; Young, Evangeline F. Y.

Author_Institution

Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Shatin, China

fYear

2013

fDate

May 29 2013-June 7 2013

Firstpage

1

Lastpage

6

Abstract

Due to a significant mismatch between the objectives of wirelength and routing congestion, the routability issue is becoming more and more important in VLSI design. In this paper, we present a high quality placer Ripple 2.0 to solve the routability-driven placement problem. We will study how to make use of the routing path information in cell spreading and relieve congestion with tangled logic in detail. Several techniques are proposed, including (1) lookahead routing analysis with pin density consideration, (2) routing path-based cell inflation and spreading and (3) robust optimization on congested cluster. With the official evaluation protocol, Ripple 2.0 outperforms the top contestants on the ICCAD 2012 Contest benchmark suite.

Keywords

VLSI; integration; network routing; optimisation; ICCAD 2012 Contest benchmark suite; VLSI design; global router integration; high quality placer Ripple 2.0; high quality routability-driven placement; lookahead routing analysis; pin density consideration; robust optimization; routing congestion; routing path-based cell inflation; tangled logic; wirelength congestion; Equations; Layout; Metals; Optimization; Routing; Upper bound; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE

Conference_Location

Austin, TX

ISSN

0738-100X

Type

conf

Filename

6560745