Effect of aging on power integrity of digital integrated circuits

Author

Boyer, A. ; Ben Dhia, S.

Author_Institution

LAAS, Univ. de Toulouse, Toulouse, France

fYear

2013

fDate

3-5 April 2013

Firstpage

1

Lastpage

5

Abstract

Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity of digital integrated circuits and clarifying its origin. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip are combined with electric stress to characterize the influence of aging on power integrity. Simulation based on ICEM modeling modified by an empirical coefficient in order to take into account the circuit aging is proposed to model the evolution of the power integrity induced by device aging.

Keywords

CMOS digital integrated circuits; ageing; integrated circuit measurement; integrated circuit modelling; integrated circuit testing; power integrated circuits; CMOS technology; ICEM modeling; device aging; digital integrated circuit aging; electric stress; electromagnetic emission; empirical coefficient; on-chip measurement; power integrity; power supply voltage; size 90 nm; test chip; Aging; CMOS integrated circuits; CMOS technology; Clocks; Geometry; MOS devices; Switches; ICEM modelling; Integrated circuits; accelerated aging; power integrity;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Workshop (LATW), 2013 14th Latin American

Conference_Location

Cordoba

Print_ISBN

978-1-4799-0595-9

Type

conf

DOI

10.1109/LATW.2013.6562681

Filename

6562681