DocumentCode
621297
Title
Bidirectional interconnect design for low latency high bandwidth NoC
Author
Kumar, Ravindra ; Deshpande, H. ; Choi, GanHo ; Sprintson, Alex ; Gratz, Paul
Author_Institution
Dept. of Electr. & Comput. Eng., Texas A & M Univ., College Station, TX, USA
fYear
2013
fDate
29-31 May 2013
Firstpage
215
Lastpage
218
Abstract
This paper presents a bidirectional interconnect design which achieves significant reduction in area and power by allowing for simultaneous transmission and reception of signals on a single interconnect segment. The proposed interconnect design achieves twice the throughput with the same link width. We have modeled the bi-directional link on the 7×7 cycle accurate NoC design. We have explored the latency for synthetic and realistic SPLASH-2 benchmarks. Synthetic benchmark results show that bidirectional design does exceedingly well in high congestion. Combination of realistic benchmarks shows that bidirectional design does much better with latency whenever the injection level of the combined benchmark is higher.
Keywords
integrated circuit design; integrated circuit interconnections; network-on-chip; NoC; SPLASH-2 benchmarks; bidirectional interconnect design; bidirectional link; synthetic benchmark; Benchmark testing; Delays; Integrated circuit interconnections; Inverters; MOS devices; Repeaters; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
IC Design & Technology (ICICDT), 2013 International Conference on
Conference_Location
Pavia
Print_ISBN
978-1-4673-4740-2
Electronic_ISBN
978-1-4673-4741-9
Type
conf
DOI
10.1109/ICICDT.2013.6563340
Filename
6563340
Link To Document