Signal integrity issues due to ESD events in high-speed CMOS comparator

Author

Nicuta, Ana-Maria ; Bicleanu, P. ; Salceanu, Andrei

fYear

2013

fDate

23-25 May 2013

Firstpage

1

Lastpage

6

Abstract

This paper is mainly focused on analyzing the behavior of the output data of a CMOS latched comparator subjected to the Human Body Model (HBM) Electrostatic Discharge (ESD) test event. The importance of the comparator circuit in the applications of data transmission is illustrated. Several tests using the Cadence IC 5.3 software were carried out in order to investigate the accuracy of the output data signal. The tests were computed for the high and low level of the clock. The malfunction of the comparator structure due to the effects of the electrostatic field is investigated. The functioning of the circuit was improved by adding decoupling capacitors with protective properties.

Keywords

CMOS logic circuits; clocks; comparators (circuits); data analysis; electronic engineering computing; electrostatic discharge; flip-flops; logic testing; Cadence IC 5.3 software; ESD events; data transmission; decoupling capacitors; electrostatic field effects; high-speed CMOS latched comparator; human body model electrostatic discharge test event; output data behavior analysis; signal integrity issues; CMOS integrated circuits; Capacitors; Clocks; Delays; Electrostatic discharges; Integrated circuit modeling; Testing; CMOS comparator; electrostatic discharge; high-speed; signal integrity;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Topics in Electrical Engineering (ATEE), 2013 8th International Symposium on

Conference_Location

Bucharest

Print_ISBN

978-1-4673-5979-5

Type

conf

DOI

10.1109/ATEE.2013.6563353

Filename

6563353