A modular and generic router TLM model for speedup network-on-chip topology generation

Networks-on-chip represent promising communication infrastructures for highly integrated circuits to deal with future systems design challenges, such as interconnection difficulties, design productivity, and power consumption. Given the difficulties associated with the design of network on chip and the necessary time to validate the simulation network topology, or the choice of network topology before the implementation at RTL level, the Transaction-level modeling has been proposed as a framework which allows rapid exploration of several networks topology containing different descriptions of system components. The Transaction-level represents a modeling technique that is intended to separate the specification of computation and communication while providing efficient methods to implement the various elements at different levels of abstraction. This paper introduces a library of generic TLM models of router components that allow constructing several types of router which can be used later to construct several network on chip topologies for performance evaluation purpose. It allows taking decision of the best topology for a given traffic or application target. To prove our approach, several router types are proposed based on these models of components and are used to build a mesh and STAR-RING network on chip at transaction level.