Performance and power consumption analysis of memory efficient 3D network-on-chip architecture

With the rapid development of the technology of 3D IC and Network-on-Chip (NoC) technology, 3D NoC emerged and drew more and more attention of researchers in recent years. But the issues of memory organization and power consumption have become two great challenges in the design of 3D NoC. This paper proposed three kinds of memory efficient 3D NoC architecture called core, corner and windows in order to achieve better performance and lower power consumption for the system. A simulation platform of 3D NoC is built with a systematical modeling language -SystemC to evaluate the performance. The experiment result shows that when compared with other two traditional 3D NoC memory architecture perlayer and mixed, two 3D NoC architectures we proposed can gain better performance and lower power consumption respectively.