Design of a low power network interface for Network on chip

Author

Swaminathan, Karthik ; Lakshminarayanan, G. ; Lang, Fengkai ; Fahmi, Muhammad ; Seok-Bum Ko

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Saskatchewan, Saskatoon, SK, Canada

fYear

2013

fDate

5-8 May 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, a low power flexible Network Interface (NI) Architecture for Network on chip (NoC) is proposed. The flexible run time configuration controller in the proposed NI plays a vital role to reduce the power by enabling and disabling the entire asynchronous First In First Outs (FIFOs) based on the traffic conditions between the router and the processing elements (PE). The NI has been implemented in Xilinx Virtex-5 XC5VLX110T FPGA. Experimental results show that the proposed low power NI offers a power improvement of 37%, when both FIFOs are inactive and 32%, when only one FIFO is active.

Keywords

field programmable gate arrays; low-power electronics; network interfaces; network-on-chip; FIFO; Xilinx Virtex-5 XC5VLX110T FPGA; asynchronous first in first out; flexible run time configuration controller; low power NI; low power flexible network interface architecture; network on chip; power improvement; processing elements; traffic conditions; Clocks; Computer architecture; IP networks; Network interfaces; Nickel; Ports (Computers); System-on-chip; Asynchronous FIFO; Network Interface; Network on Chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering (CCECE), 2013 26th Annual IEEE Canadian Conference on

Conference_Location

Regina, SK

ISSN

0840-7789

Print_ISBN

978-1-4799-0031-2

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2013.6567787

Filename

6567787