A 10-b, 300-MS/s power DAC with 6-Vpp differential swing

Author

Mehrjoo, Mohammad S. ; Buckwalter, James F.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, La Jolla, CA, USA

fYear

2013

fDate

2-4 June 2013

Firstpage

163

Lastpage

166

Abstract

A 10-bit digital-to-analog converter (DAC) is presented that delivers 6-Vpp into a 100-Ω differential load. The circuit is implemented in 45-nm CMOS SOI, which provides benefits for using a FET-stack current buffer. The measured DNL is better than 0.44 LSB. The DAC consumes 476 mW and achieves a peak SFDR of 54.4 dB and a minimum IM3 of -55.6 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a highresolution (>8b), high-speed (>100MS/s) DAC.

Keywords

CMOS integrated circuits; digital-analogue conversion; field effect transistors; silicon-on-insulator; CMOS SOI; DNL; FET-stack current buffer; LSB; differential load; differential swing; digital-to-analog converter; peak SFDR; power 476 mW; power DAC; power efficiency; resistance 100 ohm; size 45 nm; voltage 6 V; word length 10 bit; CMOS integrated circuits; Computer architecture; Impedance; Linearity; Microprocessors; Resistance; Transistors; DAC; current-steering; digital-to-analog converter;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Frequency Integrated Circuits Symposium (RFIC), 2013 IEEE

Conference_Location

Seattle, WA

ISSN

1529-2517

Print_ISBN

978-1-4673-6059-3

Type

conf

DOI

10.1109/RFIC.2013.6569550

Filename

6569550