DocumentCode
626470
Title
MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI
Author
Natsui, Masanori ; Hanyu, Takahiro ; Sakimura, Noboru ; Sugibayashi, Tadahiko
Author_Institution
Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan
fYear
2013
fDate
19-23 May 2013
Firstpage
105
Lastpage
109
Abstract
A cell-based design flow for MTJ/MOS-hybrid logic circuits is presented towards the realization of practical-scale logic LSI based on nonvolatile logic-in-memory architecture. Newly-developed supplementary design tools including a precise MTJ device model enable to design MTJ/MOS-hybrid logic´s intellectual properties (IPs) accurately. By the use of the IPs, various pattern layouts of the MOS and MTJ/MOS-hybrid logic-circuit cells can be automatically synthesized. The effectiveness of the proposed design flow is demonstrated through typical arithmetic-circuit design examples with a nonvolatile storage capability.
Keywords
MIS devices; logic circuits; logic design; magnetic tunnelling; random-access storage; IP; MTJ device model; MTJ-MOS-hybrid logic intellectual properties; MTJ-MOS-hybrid logic-circuit cell-based design flow; arithmetic-circuit design; magnetic-tunnel-junction; newly-developed supplementary design tools; nonvolatile logic-in-memory LSI; practical-scale logic LSI; Adders; Hardware design languages; Integrated circuit modeling; Large scale integration; Layout; Magnetic tunneling; Nonvolatile memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location
Beijing
ISSN
0271-4302
Print_ISBN
978-1-4673-5760-9
Type
conf
DOI
10.1109/ISCAS.2013.6571793
Filename
6571793
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