Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD cache for power reduction

Power constraint for modern processors becomes a very serious problem with the increasing core counts and cache capacity in multi/many core processors. Compared with processing cores with mature techniques like DVFS to alleviate the situation, last level cache which consume largest portion of processor chip needs effective power management strategy. In this paper, we explore the feasibility of Near-Threshold Voltage(NTV) SRAM and Multi-Voltage Domain (Multi-VDD) for power reduction in large capacity cache. To prevent data corruption in cache, we propose redundancy-based data salvaging technique for fault recovery. To solve the dilemma of power reduction and reliability guarantee, we try to match vulnerable/invulnerable data sets to high/low voltage domains. Different from previous work, we take into consideration multi-bit errors and redundancy masking effects in Multi-VDD cache. Experimental results show that our Multi-VDD cache achieves considerable improvements in energy efficiency.