Logic-on-logic partitioning techniques for 3-dimensional integrated circuits

Diminishing returns from transistor scaling, increasing interconnect delay, and the need for high device density and high energy efficiency are pushing the semiconductor industry in the direction of 3-dimensional integrated circuits (3DICs). A homogeneously integrated, logic-on-logic stacked 3DIC has the potential to be a cost-effective solution for these challenges as well as for chip security. However, this emerging integration platform currently suffers from a lack of standard CAD tool support and a 3DIC design flow to build efficient 3DICs. The work presented in this paper proposes new design partitioning techniques to smartly split any given design across various layers to build a 3DIC. These techniques reduce the search space for optimal partitioning by several times depending on the design. Further, a “design for 3D” approach is introduced, which can be used to build powerful custom 3DICs. Finally, as an example, two different 3DICs of a floating point unit are implemented using the proposed partitioning methods and the design flow. Results show an increase in speed of up to 7% and 41.5% reduction in chip footprint for even this small design.