Analog and digital approaches for an energy efficient low complexity channel decoder

This paper presents a study of analog and digital versions of a low complexity channel decoder to investigate the overall performance of both circuits in 65nm CMOS for moderate bit rate applications. Both decoding circuits realize the corresponding decoding algorithm for the convolutional codes generated by the well known 4-state (7,5)₈ encoder. The two digital and analog implementations are then analyzed for power consumption, offered coding gain, required silicon area and energy efficiency. The simulations show that the analog circuit outperforms its digital version by a factor of 10X at nominal supply voltage for the same throughputs. Furthermore, the analog implementation is 4.6 times smaller in area than its counterpart.