DocumentCode
628492
Title
Yield and reliability in 3D interconnect and WLP — Ultra thin chip stacking
Author
Luesebrink, Helge ; Pares, G. ; Attard, A. ; Schnegg, F. ; Klug, G.
Author_Institution
PVA Tepla AG Plasma Syst. Bus. Unit, Kirchheim, Germany
fYear
2013
fDate
28-31 May 2013
Firstpage
918
Lastpage
921
Abstract
This paper discusses the preconditions of thinned wafer with plasma back side stress relief (BSR) and chip side healing (CSH) processes applied in order to improve die strength allowing for stacking via pick and place preventing yield loss due to die cracking. As wafer thinning and singulating (dicing) leave scattered process marks (kerfs, chipping, micro cracks) on the chip, the thin die is prone to cracking when released from the wafer tape during a pick and place process.
Keywords
integrated circuit interconnections; integrated circuit reliability; microassembling; microcracks; 3D interconnect; BSR; CSH; WLP; chip side healing; die cracking; die strength; microcracks; plasma back side stress relief; reliability; thinned wafer; ultra thin chip stacking; wafer tape; wafer thinning; Face; Plasmas; Reliability; Silicon; Stacking; Stress; Surface treatment;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location
Las Vegas, NV
ISSN
0569-5503
Print_ISBN
978-1-4799-0233-0
Type
conf
DOI
10.1109/ECTC.2013.6575684
Filename
6575684
Link To Document