An innovative embedded interposer carrier for high density interconnection

It is well known that 3DIC integration is the next generation semiconductor technology with the advantages of small form factor, high performance and low power consumption. However the device TSV process and design rules are not mature. Assembly the chips on top of the Si interposer is the current most desirable method to achieve the requirement of good performance. In this study, a new packaging concept, the Embedded Interposer Carrier (EIC) technology was developed. It aims to solve some of the problems facing current interposer assemble issues. It eliminates the joining process of silicon interposer to the laminate carrier substrate. The concept of EIC is to embed one or multiple interposer chips into the build-up dielectric layers in the laminated substrate. The process development of EIC structure is investigated in this paper. EIC technology not only can shrink an electronic package and system size but also provide a better electronic performance for high-bandwidth applications. EIC technology can be one of the potential solutions for 3D System-in-Package.