Characterization of a low-power 6.4 Gbps DDR DIMM memory interface system

Author

Kollipara, R. ; Chang, Silvia ; Madden, Chris ; Hai Lan ; Gopalakrishnan, Liji ; Best, S. ; Yi Lu ; Bangalore, S. ; Kumar, Ganapathy E. ; Venkatesan, P.K. ; Vyas, Kirti ; Prabhu, K. ; Kaviani, K. ; Bucher, Matthias ; Lei Luo

Author_Institution

Rambus Inc., Sunnyvale, CA, USA

fYear

2013

fDate

28-31 May 2013

Firstpage

1362

Lastpage

1371

Abstract

A memory system that meets the bandwidth, power efficiency, and capacity needs of future computing systems is presented in this paper. A 6.4 Gbps single-ended DDR memory interface for the controller and the DRAM was designed in a 28-nm CMOS process for a main memory system with dual-rank DIMMs. The architecture features a novel clocking scheme, per-pin timing adjustment, dynamic point-to-point signaling topology, and near ground signaling. The system V-T budget simulations and the characterization results of the fabricated memory interface are presented.

Keywords

CMOS memory circuits; memory architecture; CMOS process; DDR DIMM memory interface system; computing system; dual rank DIMM; dynamic point to point signaling topology; near ground signaling; per-pin timing adjustment; power efficiency; single ended DDR memory interface; system V-T budget simulation; Clocks; Impedance; Noise; Random access memory; Synchronization; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Conference_Location

Las Vegas, NV

ISSN

0569-5503

Print_ISBN

978-1-4799-0233-0

Type

conf

DOI

10.1109/ECTC.2013.6575751

Filename

6575751