DocumentCode
628654
Title
A new 2.5D TSV package assembly approach
Author
Yuan Lu ; Wen Yin ; Bo Zhang ; Daquan Yu ; Lixi Wan ; Dongkai Shangguan ; Guofeng Xia ; Fei Qin ; Mao Ru ; Fei Xiao
Author_Institution
Nat. Center for Adv. Packaging, Wuxi, China
fYear
2013
fDate
28-31 May 2013
Firstpage
1965
Lastpage
1969
Abstract
Just in few years, three-dimensional (3D) packaging technologies have attracted much more attention. With emergence of through-silicon via (TSV) technology, silicon-based device integrations, the TSV´s, have become the main stream of 3D packaging technologies. TSV´s can be further classified as 2.5D and 3D TSV´s. For 2.5D TSV package assembly, since multiple components involved, there are normally two assembly process approaches, i.e., from “Top-to-Bottom” (TOB), or from “Bottom-to-Top (BOT). Each approach has its own pros and cons. From stress minimization aspect, TOB is more desirable. But from packaging assembly easiness viewpoint, BOT is more practical and thus has been mainly utilized. To overcome these dilemmas occurred in 2.5D TSV package assembly, a new assembly process approach, called new TOB (n-TOB), has been developed. Instead of bonding the chip onto the interposer, the n-TOB starts out with precisely bonding the interposer onto the chip with using a specially-designed eccentric-axis pickup tip which also effectively protects the flip chip C4 bumps on the interposer backside during bonding. Finite-element (FE) simulation and reliability tests were employed to assess the effectiveness and impact of this new assembly approach on 2.5D TSV packages. The assessment results show that n-TOB is feasible with at least the same performance in both package assembly and reliability.
Keywords
finite element analysis; flip-chip devices; integrated circuit bonding; integrated circuit packaging; integrated circuit reliability; microassembling; three-dimensional integrated circuits; 2.5D TSV package assembly; 3D packaging technology; assembly process; bottom-to-top assembly; finite element simulation; flip chip C4 bump; interposer backside; interposer bonding; reliability test; silicon based device integration; through-silicon via technology; top-to-bottom assembly; Assembly; Bonding; Flip-chip devices; Reliability; Silicon; Substrates; Through-silicon vias;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location
Las Vegas, NV
ISSN
0569-5503
Print_ISBN
978-1-4799-0233-0
Type
conf
DOI
10.1109/ECTC.2013.6575847
Filename
6575847
Link To Document