3D IC-package-board co-analysis using 3D EM simulation for mobile applications

3D IC based systems necessitate a chip-package co-design approach since the TSV response in the chip stack can propagate into the package. In this work, we demonstrate a chip-interposer co-analysis methodology that includes the 3D CAD model of the 3D IC and compare this to the conventional analysis techniques. Our findings demonstrate that the coupling between signal TSV´s in the chip stack has a significant impact on the overall channel response and needs to be carefully modeled in order to obtain accurate results.