System-level modeling and reliability analysis of microprocessor systems

Author

Chang-Chih Chen ; Milor, Linda

Author_Institution

Sch. of Electr. & Comptuer Eng., Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2013

fDate

13-14 June 2013

Firstpage

178

Lastpage

183

Abstract

In this paper, we have developed a framework to study wearout of state-of-the-art microprocessor systems. Taking into account the detailed thermal and electrical stress profiles, which are determined by running benchmarks on the system, we present a methodology to accurately estimate the lifetime due to each mechanism. The lifetime-limiting blocks and paths of a circuit are highlighted using standard benchmarks.

Keywords

integrated circuit modelling; integrated circuit reliability; microprocessor chips; electrical stress profiles; lifetime-limiting blocks; microprocessor systems; reliability analysis; system-level modeling; thermal stress profiles; Benchmark testing; Degradation; Dielectrics; Human computer interaction; Logic gates; Microprocessors; Stress; aging; backend time-dependent dielectric breakdown; electromigration; gate oxide breakdown; hot carrier injection; microprocessor reliability; negative bias temperature instability; positive bias temperature instability; stress migration; stress-induced voiding; time-dependent dielectric breakdown; wearout;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Sensors and Interfaces (IWASI), 2013 5th IEEE International Workshop on

Conference_Location

Bari

Print_ISBN

978-1-4799-0039-8

Type

conf

DOI

10.1109/IWASI.2013.6576097

Filename

6576097