Experimental analysis and modeling of self heating effect in dielectric isolated planar and fin devices

Field Effect Transistors on SOI offer inherent capacitance and process advantages. The flow of heat generated at the drain junction may be impeded by dielectric isolation but an assessment must also account for conduction of heat through the gate stack and through the device contacts, and its impact on device characteristics should be captured by the scalable model to enable accurate circuit design. A quantitative comparison to 45nm planar SOI shows that while the scaled FinFET on dielectric devices show higher normalized thermal resistance, as expected from device scaling, the characteristic time constant for self heating is still well below the operating frequency of typical logic circuits, hence resulting in negligible self heating effect. For cases where the self heating becomes a factor, e.g., in high-speed I/O circuits, the same design methods can be applied for both planar and FinFET devices on dielectric isolation.