Design of control circuit for adaptive flash ADC

Author

Chandekar, O. ; Kharbikar, Tushar ; Bhosale, P. ; Palsodkar, P.P.

Author_Institution

Priyadarshini Indira Gandhi Coll. of Eng., Nagpur, India

fYear

2013

fDate

3-5 April 2013

Firstpage

673

Lastpage

677

Abstract

This paper presents a proposed design of Peak Detector and Sub-Flash architecture for adaptive ADC. The control circuits are developed for Adaptive Resolution for Flash ADC. Peak detector circuits will consist of peak detector for variable resolution and sub-flash architecture for reconfigurability. The voltages from the Bias block are used to provide a control voltage for Peak Detector circuits. The Transient analysis for peak detector circuits are tested for pulse and sinusoidal input voltage and the settling time is reported to be 5ns and 10ns. For reconfigurability the vin is compared with Bias Block voltages for achieving the resolution i.e, 4 bit, 5 bit, 6 bit respectively.

Keywords

analogue-digital conversion; driver circuits; peak detectors; transient analysis; adaptive flash ADC; adaptive resolution; analog-digital converter; bias block; control circuit; control voltage; peak detector circuit; pulse voltage; sinusoidal input voltage; subflash architecture; transient analysis; CMOS integrated circuits; Detectors; Gain; MOSFET circuits; Rails; Signal resolution; Transient response; Adaptivity; Peak Detector; Reconfigurable; Variable Resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Signal Processing (ICCSP), 2013 International Conference on

Conference_Location

Melmaruvathur

Print_ISBN

978-1-4673-4865-2

Type

conf

DOI

10.1109/iccsp.2013.6577140

Filename

6577140