Racetrack memory based reconfigurable computing

Reconfigurable computing provides a number of advantages such as low R&D cost and design flexibility compared with application specific logic circuits; however its low power efficiency and logic density limit greatly its wide application. One of the major reasons of this shortcoming is the SRAM based configuration memory, which occupies large die area and consumes high static power. The later is more severe due to the rapidly increasing sneak currents, which are intrinsic and become worse following the fabrication node shrinking. Racetrack memory is one of emerging non-volatile memory technologies under intense investigation and promises ultra-high density, non-volatility and low power. In this invited paper, we present the design of racetrack memory based reconfigurable computing. By using a racetrack memory compact model and design kit 28 nm, mixed simulation results show its high density and low power performance compared with conventional SRAM based reconfigurable computing.