An ultra low power, reconfigurable, multi-standard transceiver using fully digital PLL

Author

Chakraborty, Shiladri ; Parikh, Viral ; Sankaran, S. ; Motos, Tomas ; Fikstvedt, Oddgeir ; Marienborg, Jan-Tore ; Griffith, D. ; Prathapan, Indu ; Nagaraj, Kanthi ; Zhang, Fang ; Smith, Ross ; Budziak, Walter ; Sundar, Shyam ; Cruise, P.

Author_Institution

Texas Instrum. Inc., Dallas, TX, USA

fYear

2013

fDate

12-14 June 2013

Abstract

This paper presents an ultra low power reconfigurable, multi-standard (IEEE802.15.4, BLE, 5Mbps proprietary) ISM2.4GHz band transceiver compliant to FCC, ETSI class 2 and ARIB regulations. It uses a DPLL with counter based area and power efficient re-circulating TDC, current reuse low area DCO, dynamic divider, class-AB PA, and fully integrated LDOs. The RX is reconfigurable between zero-IF/low-IF along with antenna diversity. The transceiver consumes 3.5mA (TX), 3.1mA (RX) from 3.0V battery with on-chip DCDC converter, and occupies 1.1mm2 in 65nm CMOS process. The RX front-end provides 42dB gain, 6dB NF, and -34dBm input P1dB.

Keywords

UHF oscillators; UHF power amplifiers; digital phase locked loops; radio transceivers; ARIB regulations; CMOS process; DPLL; ETSI class 2; FCC; RX front-end; antenna diversity; class-AB PA; current 3.5 mA; current reuse low area DCO; digital PLL; dynamic divider; frequency 2.4 GHz; fully integrated LDO; gain 42 dB; multistandard transceiver; on-chip DC-DC converter; power efficient re-circulating TDC; size 65 nm; ultralow power reconfigurable transceiver; ultralow power transceiver; voltage 3.0 V; CMOS integrated circuits; Frequency modulation; Image edge detection; Low-power electronics; Mixers; Spatial diversity; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578642