Putting the die contour back - Methods in advanced sample preparation for 3D and flip-chip devices

Author

Richardson, Chuck ; Liechty, Gary ; Smith, Colin ; Karow, M.

Author_Institution

Allied High Tech Products, Rancho Dominguez, CA, USA

fYear

2013

fDate

15-19 July 2013

Firstpage

474

Lastpage

477

Abstract

Utilizing existing sample preparation techniques and/or toolsets in the typical failure analysis lab is an effective way of reducing the bottlenecks on higher-demand contour milling machines. Methodologies for faster milling on contouring machines, and use of a through-silicon measurement tool (used for measuring remaining silicon thickness), will demonstrate how to achieve higher throughput in the lab while preserving or reintroducing the device bows/warps that were present at the start.

Keywords

elemental semiconductors; flip-chip devices; integrated circuit measurement; integrated circuit reliability; integrated circuit testing; milling; milling machines; silicon; thickness measurement; 3D device; Si; contouring machines; device bows/warps; failure analysis lab; flip-chip devices; higher-demand contour milling machines; silicon thickness measurement; through-silicon measurement tool; Decision support systems; Failure analysis; Integrated circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2013 20th IEEE International Symposium on the

Conference_Location

Suzhou

ISSN

1946-1542

Print_ISBN

978-1-4799-1241-4

Type

conf

DOI

10.1109/IPFA.2013.6599203

Filename

6599203