Design and simulation of ESD-resistant ICs

Author

Axelrad, Valery

Author_Institution

Sequoia Design Syst., Inc., Woodside, CA, USA

fYear

2013

fDate

20-22 June 2013

Firstpage

29

Lastpage

40

Abstract

Robustness of modern ICs during system assembly and normal operation requires that protection circuits are built-in to prevent damage to internal circuit elements due to Electrostatic Discharge events (ESD), which can inject substantial energy into the chip. ESD protection as well as protection against other damaging events, such as latchup, is highly dependent on chip architecture and circuit design, electrical properties of interconnects and parasitic devices, and of course device design and semiconductor process technology.

Keywords

electrostatic discharge; integrated circuit design; system-on-chip; ESD-resistant IC; chip architecture; circuit design; damaging events; electrical properties; electrostatic discharge events; interconnects; latchup; normal operation; parasitic devices; protection circuits; robustness; semiconductor process technology; system assembly; Analytical models; Electrostatic discharges; Equations; Finite element analysis; Integrated circuit modeling; Mathematical model; Semiconductor process modeling; Analog Design; ESD; Latchup; Physical Design; Power Devices; Simulation; TCAD;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed Design of Integrated Circuits and Systems (MIXDES), 2013 Proceedings of the 20th International Conference

Conference_Location

Gdynia

Print_ISBN

978-83-63578-00-8

Type

conf

Filename

6613308