Heavily doped junctionless vertical slit FETs with slit width Below 20 nm

This paper reports an alternative simple fabrication process for twin gate junctionless Vertical Slit Field Effect Transistors. N-type devices have been successfully manufactured on SOI substrates with a doping density 5×10¹⁸ atoms/cm³. The devices demonstrate up to six decades of I_on/I_off ratio and a sub-threshold swing of 90 mV/decade relative to a slit width of approximately 10 nm.