Variability analysis of self-timed SRAM robustness

This paper focusses on variability analysis for analyzing the robustness of self-timed SRAM to random process variations. The paper augments our previously proposed approaches at the circuit level which provide robustness against signals that are susceptible to deadlock with analysis techniques at the transistor level to analyze the effect of the process parameters for the transistors inside the SRAM memory cells. This has been accomplished by employing a variability analysis tool, VARMA, which facilitates the job of analyzing the robustness to variation of process parameters. We have augmented the VARMA tool to use efficient multi-partitioned surface response with back-end Monte Carlo simulation to analyse the problem. The results provide a faster insight than other approaches into the effect of variation processes on circuits.