Automatic implementation of low-complexity QC-LDPC encoders

Low Density Parity Check (LDPC) codes are a special class of error correction codes widely used in communication and disk storage systems, due to their Shannon limit approaching performance and their favorable structure. In this paper an Electronic Design Automation tool for the generation of synthesizable VHDL codes, implementing low-complexity Quasi-Cyclic LDPC (QC-LDPC) encoders is presented. The designs generated by the developed tool has been proved to exhibit hardware savings and greater throughput as compared to other published QC-LDPC encoder implementations and are based on a design methodology, where the signals in many cases are hard-wired in the LUTs and the cyclic-shifters and block-memories conventionally used, are eliminated. The presented tool also offers the advantage of providing designers with the ability to study the trade-offs in maximum clock frequency, throughput, resources utilization and power consumption, between architectures with different design parameters, enabling rapid Design Space Exploration.