• DocumentCode
    646963
  • Title

    Generation of inductive invariants from register transfer level designs of communication fabrics

  • Author

    Joosten, Sebastiaan J. C. ; Schmaltz, Julien

  • Author_Institution
    Sch. of Comput. Sci., Open Univ. of the Netherlands, Netherlands
  • fYear
    2013
  • fDate
    18-20 Oct. 2013
  • Firstpage
    57
  • Lastpage
    64
  • Abstract
    Communication fabrics constitute a key component of multicore processors and systems-on-chip. To ensure correctness of communication fabrics, formal methods such as model checking are essential. Due to the large number of buffers and the distributed character of control, applying these methods is challenging. Recent advancements in the verification of communication fabrics have demonstrated that the use of inductive invariants provides promising results towards scalable verification of Register Transfer Level (RTL) designs. In particular, these invariants are key in the verification of progress properties. Such invariants are difficult to infer. So far, they were either manually or automatically derived from a high-level description of the design. Important limitations of these approaches are the need for the high-level model and the necessary match between the model and the RTL design. We propose an algorithm to automatically derive these invariants directly from the RTL design. We consider communication fabrics to be a set of message storing elements (e.g, buffers) and some routing logic in-between. The only input required by our method is a definition of when messages enter or leave a buffer. We then exploit this well-defined buffer interface to automatically derive invariants about the number of packets stored in buffers. For several previously published examples, we automatically generate the exact same invariants that were either manually or automatically derived from a high-level model. Experimental results show that the time needed to generate invariants is a few seconds even for large examples.
  • Keywords
    formal verification; multiprocessing systems; system-on-chip; RTL designs; communication fabrics; distributed character; formal methods; inductive invariants; message storing elements; model checking; multicore processors; register transfer level; routing logic; systems-on-chip; transfer level designs; Buffer storage; Educational institutions; Equations; Fabrics; Hardware; Registers; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods and Models for Codesign (MEMOCODE), 2013 Eleventh IEEE/ACM International Conference on
  • Conference_Location
    Portland, OR
  • Print_ISBN
    978-1-4799-0903-2
  • Type

    conf

  • Filename
    6670941