• DocumentCode
    648522
  • Title

    The hardware architecture and device for accurate time signal processing

  • Author

    Dostal, Jiri ; Smotlacha, Vladimir

  • Author_Institution
    Fac. of Inf. Technol., Czech Tech. Univ. in Prague, Prague, Czech Republic
  • fYear
    2013
  • fDate
    27-30 Sept. 2013
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    The paper describes architecture, design and implementation of accurate time interval counter into the FPGA (field-programmable gate array) structure. We embedded it into the specialized adaptor for time transfer over optical links. We also present achieved results of comparison with precise commercial counter SR-620.
  • Keywords
    field programmable gate arrays; signal processing; FPGA; field-programmable gate array structure; hardware architecture; hardware device; optical links; specialized adaptor; time signal processing; time transfer;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Test Symposium, 2013 East-West
  • Conference_Location
    Rostov-on-Don
  • Print_ISBN
    978-1-4799-2095-2
  • Type

    conf

  • DOI
    10.1109/EWDTS.2013.6673107
  • Filename
    6673107
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=648522