A 1.2 mW 67.5 dB SQDR VCO-based ΣΔ ADC with Non-linearity Cancellation Technique

Shorter technology enable us to create higher speed oscillators which can provide better resolution in time domain. Therefore, a simple ADC using voltage (or current) controlled oscillator (VCO) and a counter can be implemented using this approach. Conceptually, the operation order in this ADC is similar to a conventional ΣΔ modulator. The CCO integrates frequency to produce output in the form of phase. And the number of stages in the CCO determines the quantization levels (or phase resolution). The difference of quantized phase output produces a frequency proportional to the input signal. Therefore, unlike, a conventional ΣΔ modulator no feedback is required for a first order noise shaping. In order to achieve a low power for moderate performance two key techniques have been used: a) a cross-coupled voltage to current (V/I) converter to achieve non-linearity cancellation (mainly 3^rd-order harmonic), and b) a stack structure to share current between V/I converter and CCO to reduce power. This ADC has been simulated using models of typical 130nm CMOS technology. In SPICE simulation, SQDR/SFDR of 67.5 dB/71 dB is achieved over a total signal bandwidth of 5 MHz for an input swing of 300mV (V_pp) for typical corner at room temperature. The analog blocks consumed a total of 96.5μW from a regulated 1.2V supply, whereas, the digital blocks consumed an estimated power of 1.1 mW. Since, the major circuit blocks are digital in nature, the presented circuit is highly amenable with technology scaling.