A fast radix-3 SAR analog-to-digital converter

Author

Long Chen ; Rahman, Mosaddequr ; Sha Liu ; Nan Sun

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Texas at Austin, Austin, TX, USA

fYear

2013

fDate

4-7 Aug. 2013

Firstpage

1148

Lastpage

1151

Abstract

This paper presents a new radix-3 successive approximation register (SAR) analog-to-digital converter (ADC). Our proposed radix-3 SAR ADC can generate 1.6N binary bits during N comparison cycles. The radix-3 SAR ADC is 60% faster than the conventional radix-2 SAR ADC. Our prototypes are implemented with 4 and 7 ternary bits using 180nm CMOS technology. They can achieve a signal-to-quantization-noise ratio (SQNR) of 39 dB and 66 dB which are equivalent to 6.2 and 10.7 binary bits respectively.

Keywords

CMOS integrated circuits; analogue-digital conversion; digital arithmetic; CMOS technology; fast radix 3 SAR analog to digital converter; signal to quantization noise ratio; size 180 nm; successive approximation register; ternary bits;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (MWSCAS), 2013 IEEE 56th International Midwest Symposium on

Conference_Location

Columbus, OH

ISSN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2013.6674856

Filename

6674856

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=649383