DocumentCode
649927
Title
Design, analysis and FPGA implementation LDPC codes with BCH codes
Author
Muthammal, R. ; Madhane, S. Srinivasa Rao
Author_Institution
St. Peter´s Univ., Chennai, India
fYear
2013
fDate
3-3 July 2013
Firstpage
242
Lastpage
244
Abstract
In this work, a analysis is performed between LDPC and BCH codes, the BCH codes[1] and LDPC codes both being an error correcting codes that can be used in wireless standards, by implementing these two error correcting codes in FPGA we analyze the Architectures of Error correcting codes in order to show that LDPC is having low area and less power than BCH codes.
Keywords
BCH codes; error correction codes; field programmable gate arrays; parity check codes; BCH codes; Bose-Chaudhuri-Hocquenghem codes; FPGA; LDPC codes; error correcting codes; field programmable gate arrays; low density parity check codes; BCH Codes; FPGA; LDPC;
fLanguage
English
Publisher
ieee
Conference_Titel
Current Trends in Engineering and Technology (ICCTET), 2013 International Conference on
Conference_Location
Coimbatore
Print_ISBN
978-1-4799-2583-4
Type
conf
DOI
10.1109/ICCTET.2013.6675957
Filename
6675957
Link To Document