Design and analysis of various slice reduction algorithm for low power and area efficient FIR filter

DA architecture synthesizes multiplier blocks with low hardware requirement suitable for implementation as part of full parallel finite impulse response (FIR) filters is presented in this paper. Then new add and shift method is introduced for low power, this method is used for SDR. SDR is fast becoming a crucial element of wireless technology the use of SDR technology is predicted to replace many of the traditional methods of implementing transmitters and receivers while offering a wide range of advantages including adaptability, reconfigurability, and multifunctionality encompassing modes of operation, radio frequency bands, air interfaces, and waveforms. Software-defined radio (SDR) refers to wireless communication in which the transmitter modulation and the receiver demodulation are both generated through software. The main advantage of this approach is flexibility, as the software runs on one common hardware platform for any type of receiver configuration. The most computationally intensive part of the wideband receiver of a software defined radio (SDR) is the intermediate frequency (IF) processing block. The proposed reconfigurable synthesizes multiplier blocks offer significant savings in area over the traditional multiplier blocks for high-speed digital signal processor (DSP) systems are implemented on field programmable gate array (FPGA) hardware platforms. Various slice reduction algorithm like RSG, MSG, Add and Shift and DA algorithm are designed to get the low power and area efficient fir filter.