A Power Model Combined of Architectural Level and Gate Level for Multicore Processors

Low power consumption is becoming a critical factor for multicore processors. As the multicore processor design complexity increases, power estimation for multicore processors has gained more importance. This paper presents a new power model combined of architectural level and gate level for multicore processors. The model maps the multicore processors to a combination of building blocks, and estimates the gate-level power of these blocks using parameterized RTL. Then, the power numbers are made in the form of look-up tables, and integrated in architecture simulators. The experiments show that for peak power estimation, an excellent accuracy has been reached and simulation performance is greatly improved compared to the gate level.