DocumentCode
654962
Title
[2010] Facing the Exascale Energy Wall
Author
Kogge, Peter M. ; La Fratta, Patrick ; Vance, Megan
Author_Institution
Dept. of Comput. Sci. & Eng., Univ. of Notre Dame, Notre Dame, IN, USA
fYear
2010
fDate
17-19 Jan. 2010
Firstpage
51
Lastpage
58
Abstract
A recent report focused on the technical challengesin advancing from today\´s "petascale" systems to "exascale."Power, or more accurately energy, was a dominant challenge. This paper briefly reviews the energy challenge for exascaled sized systems, with an emphasis on the relatively enormous energy costs of referencing operands from the memory hierarchy. Then, usinga key step from the LINPACK benchmark, we investigate twodifferent approaches to reducing such costs: one which migratescomputations up from the host to higher levels of the hierarchy,and another in moving the whole computation closer to memory. Both show significant improvements over architecture as usual.
Keywords
DRAM chips; memory architecture; multiprocessing systems; power aware computing; LINPACK benchmark; exascale energy wall; memory hierarchy; Instruction sets; Microprocessors; Multicore processing; Random access memory; Silicon; System-on-chip; memory wall; multi-core; parallel processing; power;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Architecture for Future Generation High Performance (IWIA), 2010 International Workshop on
Conference_Location
Kona, HI
ISSN
1527-1366
Type
conf
DOI
10.1109/IWIA.2010.9
Filename
6685626
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