A 2.4-µA 868-MHz low latency wake-up receiver for strong interference channels

This paper describes an innovative approach for integrated ultra-low current wireless receivers for UHF bands in a 180-nm CMOS technology. The classical method of slow periodic switching off of the receiver was picked up, essentially enhanced and applied to a superheterodyne receiver topology. A novel fast sampling pulse operation method for ultra low power integrated receivers is presented meeting both short reaction time and very low power consumption requirements. In addition, the receiver was designed for radio channels with strong interferers. The presented ASIC comprises both an analogue front-end and two digital 31 bit correlating decoders. The current consumption of the fabricated prototype is 2.4 μA at 3 volts supply voltage with a reaction time of 485 ms.