Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs

Author

Hashizume, Masaki ; Konishi, Tsuyoshi ; Yotsuyanag, Hiroyuki ; Shyue-Kung Lu

Author_Institution

Inst. of Technol. & Sci., Univ. of Tokushima, Tokushima, Japan

fYear

2013

fDate

18-21 Nov. 2013

Firstpage

13

Lastpage

18

Abstract

A testable design method for electrical testing is proposed in this paper to detect open defects occurring at interconnects between dies in a 3D IC and locate the defective interconnects. An IEEE 1149.1 test circuit is utilized to provide a test input vector to a targeted interconnect in the electrical tests. Feasibility of the electrical tests is evaluated by Spice simulation and some experiments with a prototyping IC. It is shown by the experiments that an open defect can be detected at a test speed of 1MHz.

Keywords

SPICE; design for testability; integrated circuit interconnections; integrated circuit testing; three-dimensional integrated circuits; 3D IC; IEEE 1149.1 test circuit; Spice simulation; electrical testing; electrical tests; frequency 1 MHz; open defects; testable design; Discrete Fourier transforms; Integrated circuit interconnections; Integrated circuit modeling; Layout; Three-dimensional displays; Vectors; 3D IC; Design for Testability; Electrical Test; Open Defect; Through-Silicon Via;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Symposium (ATS), 2013 22nd Asian

Conference_Location

Jiaosi Township

ISSN

1081-7735

Type

conf

DOI

10.1109/ATS.2013.13

Filename

6690607