DocumentCode
658552
Title
Mid-bond Interposer Wire Test
Author
Li-Ren Huang ; Shi-Yu Huang ; Kun-Han Tsai ; Wu-Tung Cheng ; Sunter, Sedat
Author_Institution
Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
2013
fDate
18-21 Nov. 2013
Firstpage
153
Lastpage
158
Abstract
Testing the quality of the interposer wires in a 2.5-D stacked IC can avoid the penalty arising from bonding known-good dies to a defective interposer. However, an interposer is particularly hard to test alone due to the lack of a device layer. This paper addresses this problem by proposing amid-bond test method - in which the interposer is tested after each die is attached to the substrate. We borrow the technique of pre-bond test method for the TSV and enhance it by a length-normalization scheme to cope with interposer wires of diverse wire lengths. Simulations show that this mid-bond test method can catch a high percentage of open faults before subsequent dies are attached.
Keywords
integrated circuit testing; three-dimensional integrated circuits; 2.5-D stacked IC; TSV; amid-bond test method; interposer wires quality testing; length-normalization scheme; mid-bond interposer wire test; pre-bond test method; Capacitance; Circuit faults; Inverters; Oscillators; Resistance; Through-silicon vias; Wires; 2.5-D Stacked IC; Design for Testability; Interposer; Length Normalization; Mid-bond test; Resistive Open Fault;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium (ATS), 2013 22nd Asian
Conference_Location
Jiaosi Township
ISSN
1081-7735
Type
conf
DOI
10.1109/ATS.2013.37
Filename
6690633
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