A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS

This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation.