A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration

Author

Ba-Ro-Saim Sung ; Chang-Kyo Lee ; Wan Kim ; Jong-In Kim ; Hyeok-Ki Hong ; Ghil-Geun Oh ; Choong-Hoon Lee ; Choi, Michael ; Ho-Jin Park ; Seung-Tak Ryu

Author_Institution

KAIST, Daejeon, South Korea

fYear

2013

fDate

11-13 Nov. 2013

Firstpage

281

Lastpage

284

Abstract

A power-efficient and speed-enhancing technique for time-interleaved (TI) SAR ADCs that is assisted by a low-resolution flash ADC is presented. The 3 b MSBs achieved from a flash ADC at every clock save two decision cycles from every SAR ADC channel, resulting in a reduced number of time interleaving channels with a total 27% energy saving compared with the energy consumption of a conventional TI SAR ADC. A prototype 6 b 2 GS/s ADC in a 45 nm CMOS consumes 14.4 mW under a 1.2 V supply and achieves 5.2 ENOB_Nyq with a background offset calibration.

Keywords

CMOS integrated circuits; analogue-digital conversion; background offset calibration; decision cycles; energy consumption; flash-assisted time-interleaved SAR ADC; low-resolution flash ADC; power 14.4 mW; power-efficient technique; size 45 nm; speed-enhancing technique; time interleaving channels; voltage 1.2 V; word length 6 bit; CMOS integrated circuits; Calibration; Capacitors; Clocks; Power demand; Switches; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference (A-SSCC), 2013 IEEE Asian

Conference_Location

Singapore

Print_ISBN

978-1-4799-0277-4

Type

conf

DOI

10.1109/ASSCC.2013.6691037

Filename

6691037